In a radar system, it is known that the signal level of received signals may vary across a large dynamic range. In order to avoid false alarms and missing detection, an extraordinarily linear receiver is required in order to reliably detect weak reflection signals that are received barely above the receiver noise level (e.g. from targets with a small cross section and/or that are relatively far away such that the echo signal is returned at a very low level). A problem exists when these weak reflection signals coexist with other strong reflection signals (e.g. from nearby pedestrians mixed with nearby vehicles, say in an urban area).
When receiving strong echo/reflection signals, the radar receiver channel linearity is normally limited by the nonlinearity of millimetre (mm)Wave/radio frequency (RF) front-end circuits of the radar unit; whilst for weak reflection signals it is limited by the analog-to-digital converters' (ADC's) performance at being able to identify a small received signal (say from a distal object) from amongst one or more much larger received signals. The ADCs for high performance automotive radar sensors (sometimes referred to as radar units) are required to have ultra-low spurs levels (e.g. below −90 dBFS or even −100 dBFS) together with a wide bandwidth, low noise, low power and low latency under wide operation conditions. Designing such an ADC in order to meet such stringent small signal linearity requirements is a challenging task.
In contrast to linear amplifiers, harmonic distortions introduced by the static linearity errors (differential nonlinearity (DNL)/integral nonlinearity (INL)) of Nyquist-rate ADCs do not scale down as input signal amplitude decreases; instead it is recognised that they can stay at a similar level, noting that DNL is the differential nonlinearity and is defined by the deviation between the difference between an actual step width and the ideal value of ‘1’ LSB, whilst INL is the integral nonlinearity and is defined by the deviation of the actual ADC transfer function from the ideal one.
Referring now to FIG. 1, a known signal diagram 100 illustrates a strong input signal 112 and a weak input signal 114 of an input analog signal 110 being provided to an ADC. The ADC converts the input analog signal 110 to a range of digital output reference values 120, say for signal processing in a radar unit. As shown, only a small number 122 of digital output reference values 120 are available to describe the weak input signal 114. Consequently, the ADC conversion errors are known to have a strong signal level dependency, which leads to undesirable harmonic spurs that can cause false target detection.
The successive approximation register (SAR) ADC architecture is one of the most popular ADC architectures, as demonstrated in many publications, as the choice for achieving a good overall performance (e.g. wide bandwidth, low power, low latency). However, the small input signal linearity of the SAR ADC is limited due to the limitations presented above. FIG. 2 illustrates a known generic example block diagram of a SAR ADC 200, with operational phases and waveforms. The SAR ADC 200 includes an input 210 that is provided to a track-and-hold (T/H) circuit 214, and a sampled output provided to a comparator 216, and finally a SAR controller 218. A feedback path includes N-bit control signals 219 connected to the SAR controller 218 and a N-bit digital to analog converter (DAC) 220 arranged to convert the converted digital input signal to an analog form. A digital data output 230 is output from the SAR ADC 200 as a result of the comparator output and the determination by the SAR controller 218.
The operation of an SAR ADC 200 consists of two phases, which are repetitive as shown in 250 when the ADC is active. In a first sampling phase 260, the analog input signal is processed through the T/H circuit 214, which is normally a switched capacitor type circuit and the sampled signal (Vsampled) is held on a capacitor. Thus, when the switch transistor M1 211 turned on, the input analog signal is passed to a capacitor Cs 213 (the voltage across the capacitor follows the input signal), at the moment the switch transistor M1 211 is turned off, the signal amplitude value of this moment is stored across the capacitor Cs 213. This is also the so called tracking phase.
In a second SAR conversion phase 270, the SAR controller controls the DAC to generate an analog output signal (VDAC) 280 in order to approximate the sampled signal (Vsample) 290 in each conversion cycle. The amplitude 252 difference of the sampled signal (Vsample) 290 and the DAC output signal (VDAC) 280 is then amplified and compared by a comparator. The comparison and approximation are done sequentially over a number of cycles. At the end of the conversion phase, the DAC output signal (VDAC) 280 approximates the sampled signal (Vsample) 290 with a maximum deviation of VLSB/2 ideally. The output digital codes (Dout) represent the sampled analog signal.
The output of the N-bit DAC 220 is an analog signal expressed by:
                                          V            DAC                    ⁡                      [            i            ]                          =                              ∑                          i              =              1                                      N              C                                ⁢                                    d              ⁡                              [                                                      N                    C                                    -                  i                                ]                                      ·                          weights_a              ⁡                              [                                                      N                    C                                    -                  i                                ]                                                                        [        1        ]            Where: d[i] denotes the comparator decision with {−1, 1} at the i-th conversion step,                NC the total number of conversion cycles, and        weight_a[i] denotes the actual weights of the DAC cells (note: the weights are the ratio of values of DAC cells to that of the least significant bit (LSB) DAC cell).        
In a conventional SAR conversion, the DAC cells are switched one by one, in sequence, from the largest DAC cell to the smallest DAC cell, in order to approximate the sampled signal successively.
The ADC digital output codes can be expressed by:
                                          D            out                    ⁡                      [            i            ]                          =                              ∑                          i              =              1                                      N              C                                ⁢                                    d              ⁡                              [                                                      N                    C                                    -                  i                                ]                                      ·                          weights_d              ⁡                              [                                                      N                    C                                    -                  i                                ]                                                                        [        2        ]            Where: weight_d[i] denotes the weights used by the ADC 200 for reconstructing the digital representation of the sampled analog signal.
Ideally, the values of weight_d should be exactly the same as weight_a. However, due to the mismatch of components (transistors, capacitors, or resistors, etc.) that are used to implement DAC cells in the N-bit DAC 220, the weights used in the digital domain can deviate from the actual weights of the DAC cells. This results in DNL/INL errors that cause unwanted harmonic spurs. This error mechanism is the main source of small signal nonlinearity in Nyquist-rate ADCs.
Many published works use predefined DAC cell weights (e.g. weight_d[0: NC−1]=1, 2, 4, 8, . . . , 2{circumflex over ( )}(Nc−1)) in order to reconstruct the ADC output signal, and rely on the intrinsic matching of devices to exhibit a relatively small difference between weight_d and weight_a. A major drawback of this approach is that large components' size is needed to reduce mismatches. In order to meet the ultra-low spurs level requirement for small signals, this approach can result in an unrealistic large component size and degradation of ADC conversion speed due to the accompanied large parasitic capacitors.
There are also a number of known approaches that exploit calibration methods in order to reduce weight deviation between weight_d and weight_a, instead of relying on the intrinsic matching accuracy of DAC cells. The advantage of these calibration approaches includes a reduction of silicon area and no compromise in the ADC conversion speed at the expense of addition design complexity. In a calibration phase, the actual weight values of DAC cells are measured and stored. Instead of using weight_d, the measured DAC cells weights (weight_mea) are used to map the non-binary ADC output digital codes (Dout) to binary codes during normal operation. The errors introduced during reconstruction in the digital domain are now determined by the weight measurement accuracy (the differences between weight_mea and weight_a) in the calibration process.
However, the resulting performance from a use of calibration techniques can vary significantly. This is because the measurement and/or correction can be affected by the non-idealities of analog circuits that are involved in the calibration. The limitations for reliably achieving the ultra-low spurs level requirement for converting weak input signals include the weight value measurement accuracy being affected by noise (e.g. thermal, flicker, impulse noise), supply disturbances, crosstalk, settling, offset, and so on. Furthermore, the measurement procedure of DAC cells may be iterative (i.e. using the measured values of smaller sources to measure larger ones). Thus, errors in the measurement of small sources will propagate to the larger ones (e.g. to have 0.01% measurement accuracy in the MSB DAC cell, smaller DAC cells should have better than 0.01% measurement accuracy). Additionally, the actual weight values can vary during operation due to temperature and supply voltages drift, this can cause significant deviation from the weight values obtained in the start-up measurement (simulations have shown that this could cause over 10 dB variation in small signal linearity).
Dynamic Element Matching (DEM), dither and mismatch error shaping are popular techniques for mitigating the DAC cell mismatch problem. DEM and dither randomize DAC mismatch errors and reduce spurs at the expense of additional complexity, DEM requires complicated encoders and degrades normal operation speed, whilst the introduction of dither reduces the useful input range of the ADC. Other techniques propose DAC mismatch error shaping for oversampling SAR ADCs in order to achieve very high linearity without calibration. However, this technique requires a large oversampling factor, which greatly reduces the useful input signal bandwidth.
Thus, the inventors have identified and appreciated a number of problem areas in the use of SAR ADCs. First, the inventors have identified that mismatches between weight coefficients used for mapping the digital codes and the actual DAC cells weights lead to unwanted spurs, and limit the small signal linearity of the ADC. Secondly, switching of the first few large DAC cells is in fact redundant for small sampled signal, however, the weight deviation of the larger DAC cells still affect the output signal linearity and it is a dominant factor.
Thus, a mechanism is needed to improve SAR ADC performance, for example within a radar unit.